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Super FinSim v8.2.5
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Posts: 876
Join Date: Oct 2005
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Features: Best choice for large farms for Verilog simulation Supports the entire Verilog language, user defined primitives, specify blocks, system tasks and functions, PLI 1.0, VCD and SDF. Supports compiled, interpreted, and any mixture of compiled and interpreted simulation First mixed event and cycle driven simulator for Verilog Smart partitioner analyzes the design and decides which areas can be simulated by the Enhanced Cycle Simulation (ECS) kernel Able to handle modules with path delays as well as some RTL-level modules, and fully supports Xs and Zs as well as the entire range of Verilog strengths. Supports all popular waveform display tools including Veritools' Undertow, Cadence's Signalscan Rated the fastest Verilog simulator In the DA Solution Limited `96 benchmark FinSim was rated the fastest PC-based Verilog simulator in the ASIC & EDA benchmark. Super-FinSim runs on all popular platforms including Sun Solaris, HP UX, DEC Unix, DEC NT and PCs running Windows NT/2000, Windows 95/98/ME and Linux Add-on components include code coverage and Verilog Analyzer downlaod http://www.ceopower.com/products/simulation/ |
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